//*****************************************************************************
//*****************************************************************************
//  FILENAME: SPIM_1.h
//   Version: 2.6, Updated on 2010/4/6 at 11:27:39
//  Generated by PSoC Designer 
//
//  DESCRIPTION:
//    SPIM_1 SPIM User Module header file.
//-----------------------------------------------------------------------------
//      Copyright (c) Cypress Semiconductor 2010. All Rights Reserved.
//*****************************************************************************
//*****************************************************************************
#ifndef SPIM_1_INCLUDE
#define SPIM_1_INCLUDE

#include <m8c.h>

#pragma fastcall16  SPIM_1_EnableInt
#pragma fastcall16  SPIM_1_DisableInt
#pragma fastcall16  SPIM_1_Start
#pragma fastcall16  SPIM_1_Stop
#pragma fastcall16  SPIM_1_SendTxData
#pragma fastcall16  SPIM_1_bReadRxData
#pragma fastcall16  SPIM_1_bReadStatus

//-------------------------------------------------
// Prototypes of the SPIM_1 API.
//-------------------------------------------------
extern void  SPIM_1_EnableInt(void);
extern void  SPIM_1_DisableInt(void);
extern void  SPIM_1_Start(BYTE bConfiguration);
extern void  SPIM_1_Stop(void);
extern void  SPIM_1_SendTxData(BYTE bTxData);
extern BYTE  SPIM_1_bReadRxData(void);
extern BYTE  SPIM_1_bReadStatus(void);

// Old function prototypes, Do not use
// These will be removed in a future release
#pragma fastcall16 bSPIM_1_ReadRxData
#pragma fastcall16 bSPIM_1_ReadStatus
extern BYTE bSPIM_1_ReadRxData(void);
extern BYTE bSPIM_1_ReadStatus(void);


//-------------------------------------------------
// Constants for SPIM_1 API's.
//-------------------------------------------------

#define SPIM_1_INT_REG_ADDR                    ( 0x0e1 )
#define SPIM_1_bINT_MASK                       ( 0x80 )

//*******************************
// SPI Configuration definitions
//*******************************
#define  SPIM_1_SPIM_MODE_0            0x00      // MODE 0 - Leading edge latches data - pos clock
#define  SPIM_1_SPIM_MODE_1            0x02      // MODE 1 - Leading edge latches data - neg clock
#define  SPIM_1_SPIM_MODE_2            0x04      // MODE 2 - Trailing edge latches data - pos clock
#define  SPIM_1_SPIM_MODE_3            0x06      // MODE 3 - Trailing edge latches data - neg clock
#define  SPIM_1_SPIM_LSB_FIRST         0x80      // LSB bit transmitted/received first
#define  SPIM_1_SPIM_MSB_FIRST         0x00      // MSB bit transmitted/received first

//********************************
// SPI Status register masks
//********************************
#define  SPIM_1_SPIM_RX_OVERRUN_ERROR  0x40      // Overrun error in received data
#define  SPIM_1_SPIM_TX_BUFFER_EMPTY   0x10      // TX Buffer register is ready for next data byte
#define  SPIM_1_SPIM_RX_BUFFER_FULL    0x08      // RX Buffer register has received current data
#define  SPIM_1_SPIM_SPI_COMPLETE      0x20      // SPI Tx/Rx cycle has completed

//-------------------------------------------------
// Register Addresses for SPIM_1
//-------------------------------------------------
#pragma ioport  SPIM_1_CONTROL_REG: 0x03f                  //Control register
BYTE            SPIM_1_CONTROL_REG;
#pragma ioport  SPIM_1_SHIFT_REG:   0x03c                  //TX Shift Register register
BYTE            SPIM_1_SHIFT_REG;
#pragma ioport  SPIM_1_TX_BUFFER_REG:   0x03d              //TX Buffer Register
BYTE            SPIM_1_TX_BUFFER_REG;
#pragma ioport  SPIM_1_RX_BUFFER_REG:   0x03e              //RX Buffer Register
BYTE            SPIM_1_RX_BUFFER_REG;
#pragma ioport  SPIM_1_FUNCTION_REG:    0x13c              //Function register
BYTE            SPIM_1_FUNCTION_REG;
#pragma ioport  SPIM_1_INPUT_REG:   0x13d                  //Input register
BYTE            SPIM_1_INPUT_REG;
#pragma ioport  SPIM_1_OUTPUT_REG:  0x13e                  //Output register
BYTE            SPIM_1_OUTPUT_REG;

#endif
// end of file SPIM_1.h
